1. Field of the Invention
The present invention relates generally to dynamic random access memory devices, and more specifically to improvements in producing a layered capacitor structure for a random access memory cell.
2. Description of the Prior Art
As is well known, a memory cell used in a dynamic random access memory device (DRAM), is composed of a memory cell capacitor, such as a stacked capacitor, and a transfer transistor. In order to reduce the cost, and increase the speed of operation, the memory devices have become increasingly more miniaturized. In order to achieve this, each memory cell must occupy less space on the device. However, the cell capacitor must have roughly the same capacitance. The capacitance of a capacitor is proportional to the area of the electrodes. Thus, in order to maintain the capacitance level as the allotted area on the device becomes smaller, various new types of capacitors have been introduced, such as trench capacitors, stacked capacitors and similar devices.
U.S. Pat. No. 4,910,566 discloses an improved cell capacitor for a DRAM cell. In general, the patent discloses a memory cell capacitor consisting of a plate shaped film and a vertical projection film which are formed of doped polysilicon. The plate-shaped film and vertical projection film are formed on an interlayer insulation film. The vertical projection film is in contact with a sidewall of the plate-shaped film. With the vertical projection film, it is possible to increase the capacitance of the memory cell capacitance.
FIGS. 1 and 2 depict the general nature of the capacitor known in the prior art. In FIG. 2, a transfer transistor is shown consisting of a source 10 and drain 12, and a gate electrode 14. An insulating film 16 extends over the gate electrode. Opposite the transistor is shown a thick field oxide 18, and a gate electrode 20 of an adjacent memory cell, with an overlying insulating film 16. Positioned between the electrodes 14 and 20 is the cell capacitor consisting of a polysilicon layer formed of a horizontal plate portion 22 joined to a vertical projection portion 24. A thin insulation layer 26 overlays the cell capacitor.
The cell capacitor of U.S. Pat. No. 4,910,566 suffers from very serious shortcomings in that fabrication, as described, requires a very precise mask adjustment to form the opening over the drain region. Particularly for deep submicron technology, the tight control requirement of this patent will be more critical in order to keep the proper alignment. Also the concentrations of the dopant in the vertical projection portions 24 is low due to the limitation of ion implantation.